1. Field of the Invention
The present invention relates to three-dimensional capacitors. More particularly, the invention relates to a three-dimensional capacitor, in which a bi-layer dielectric layer is used between the electrodes.
2. Background Information
Small cell size is crucial to allow minimal chip size and thus reduce chip cost. While the integrated circuit (IC) dimensions continue to shrink down to the nanometer arena, the vertical dimensions of these nano-scale device structures do not scale due to many constraints. For example, device-scaling performance requirements limit the vertical scaling. Moreover, process integration considerations etch selectivity during dry etch, polish stop margin for chemical mechanical planarization (CMP), and defect considerations limit the thickness of films and material stacks during the fabrication of IC chips.
Traditionally, a storage charge in a cell has been increased by decreasing the dielectric thickness and/or by increasing the capacitor area. The area of the capacitors has been increased through the use of complex three-dimensional capacitor structures, such as deep cylinders, studs, and crowns. Three-dimensional capacitor structures utilize high aspect ratios in order to increase the capacitor area; however, the structures required to demonstrate this capacitance at pitches that are commensurate with future technology shrinks are becoming increasingly difficult to fabricate. Therefore, these high-aspect capacitors pose a variety of new challenges related to patterning, deposition, and etch processes, as well as mechanical stability during and after fabrication.
In order to provide the increased capacitance desired, high-dielectric materials, such as tantalum oxide (TaO) and strontium titanium oxide (SrTiO3), are often used as they tend to have a larger permittivity than low-dielectric materials such as SiO2 and Si3N4, which can also be used. However, despite the availability and use of these high-dielectric materials, a three-dimensional capacitor is still required to realize a capacitor having a large capacitance. Additionally, in three-dimensional capacitors, ruthenium (Ru) has been used for electrodes, wherein the Ru can be deposited into a patterned SiO2 hole to form a Ru electrode. However, the low solubility of Ru into SiO2 can be problematic for depositing a Ru electrode in a patterned SiO2 hole.
However, one problem with providing a three-dimensional capacitor with a Ru electrode is that high process temperatures can lead to difficulties in applying a dielectric layer to a Ru electrode. For example, if a dielectric layer of Ta2O5 were to be used with a Ru electrode, the process temperature of the Ru based capacitor should be kept below 700° C. to prevent failure of the capacitor. Temperatures above the upper limit of 700° C. could cause a high temperature anneal of the Ta2O5 and can cause a Ru electrode of the Ru-based capacitor to suffer from contact resistance failure at this temperature (higher than 700° C.). Thus, a Ru-based capacitor with a Ta2O5 dielectric layer is desirably processed at temperatures less than 700° C., which is less than desired for manufacturing purposes.